This is part of the "counter and register notes" web pages, which contain the following subtopics:
  1. Ripple counter
  2. Synchronous counter    <-- you are here
  3. Synchronous counter with reset
  4. Very simple register (parallel load)
  5. Very simple shift register (serial load)
  6. Designing a circuit which can shift or load
  7. More realistic shift register with parallel load

Synchronous counter

The input to each JK flip-flop will be an AND of the Qs of all of the lower-order flip-flops. The pulse input (clock input) goes to all flip-flops.

All of the flip-flops flip simultaneously (if they should be flipping at all this cycle), because they're all clocked by the same clock. The cumulative AND function computed on the right is a predictor function, which determines in advance whether or not the given bit should flip in the next cycle.

What about the "reset" function?
See my synchronous counter with reset, next.

This is part of the "counter and register notes" web pages, which contain the following subtopics:

  1. Ripple counter
  2. Synchronous counter    <-- you are here
  3. Synchronous counter with reset
  4. Very simple register (parallel load)
  5. Very simple shift register (serial load)
  6. Designing a circuit which can shift or load
  7. More realistic shift register with parallel load

[list of course notes topics available] [main course page]