This is part of the "counter and register notes" web pages, which contain the
following subtopics:
- Ripple counter
- Synchronous counter
- Synchronous counter with reset
- Very simple register (parallel load)
- Very simple shift register (serial load)
- Designing a circuit which can shift or load
- More realistic shift register with parallel load <-- you are here
Shift register with parallel load
Each DFF is either set to
- xi (if LOAD), or
- x(i-1) (if SHIFT), or
- yi (if (not SHIFT) AND (not LOAD))
, every cycle.
So the clocks of all of the D flip-flops can be connected into the system
master clock.
In fact, we would in practice make this even more complex, by
having separate "left-shift" and "right-shift" control lines.
The above SHIFT is a left-shift.
(You are not expected to be able to reproduce the above from memory
in a test or exam
situation, although designing such a thing should not be beyond you by the
end of the course.)
This is part of the "counter and register notes" web pages, which contain the
following subtopics:
- Ripple counter
- Synchronous counter
- Synchronous counter with reset
- Very simple register (parallel load)
- Very simple shift register (serial load)
- Designing a circuit which can shift or load
- More realistic shift register with parallel load <-- you are here
[list of course notes topics available]
[main course page]