Sample RISC machine language (assembly language)

Here is a sample hypothetical RISC-like machine language which embodies some of the instruction set design factors we've been discussing:

simple, fixed-format instructions; no complex addressing
load/store architecture
delayed branch and delayed load rules
three-register instruction format
register windows

This CPU has 120 GPRs, only 15 of which are visible at a time. The registers visible at one time are numbered R1 through R15. A JSR advances the register window by 7 and an RTS puts it back by 7.

R0 is zero; it's not a register. E.g. "MOV R3, R4" can be written "ADD R0, R3, R4". (And there is no MOV instruction.)

This means that the standard register in which a subroutine leaves a return value will be R1 -- the subroutine's R1, which will be the caller's R8. Parameters are passed in the caller's R8 through R15; parameters after the eighth are passed on the stack (very rare). These registers are then free for use by the called subroutine; it does not have to restore any of these, even those which were not used for parameters.

R0 can also be specified as a target register, when we want to throw the value away; thus VELMA's "CMP R2, R1" is written "SUB R1, R2, R0". Also note the subtraction operand order: It's always first-thing minus second-thing.

There are three instruction formats (actually, categories #2 and #3 have the same bit layout):

Tri-register instructions:
- ADD reg, reg, reg
- SUB reg, reg, reg
- MUL reg, reg, reg (one-word result)
- DIV reg, reg, reg (one-word operands, two-word result)
- IND reg0, reg1, reg2 (actually a weird load instruction -- see below)
Memory instructions:
- LOAD address, reg (like MOV address, reg) (reg may not be used or changed in the subsequent instruction)
- STORE reg, address (like MOV reg, address) (reg may not be the result of the previous instruction nor may it be changed in the subsequent instruction)
- JSR address (reg field not used) (delayed branch rule in effect)
- RTS (reg and address fields not used) (delayed branch rule in effect)
- branch instructions (BR, BGT, BLE, all of 'em) (reg field not used) (delayed branch rule in effect)
Immediate instructions:
- MOVEI n, reg
- ADDI n, reg

Our ordering for "LOAD address, reg" might be a bit odd, but it is more compatible with the assembly language we've been doing so far. And unlike in the case of a VELMA MOV, there is no ambiguity. The data movement for a LOAD, whichever order we write the operands in in the assembly syntax, is from memory to a GPR.

The IND instruction is used for indirect addressing, possibly with an offset (indexing). Its semantics are: reg2 <- M[reg0+reg1]. After an IND, reg2 may not be used or modified in the next instruction.

There is a delayed branch rule and a delayed load rule.

Here's a simple example: a set of instructions to compute C := A + B. There's really nothing very interesting to do with the delayed load slots, so we don't, except for the last.

     LOAD A, R1
     NOP  ; can't do a load in the delayed load slot, either...
     LOAD B, R2
     NOP
     ADD R1, R2, R2
     NOP  ; and you can't do STORE R2 immediately after ADD ,,R2
     STORE R2, C
     HALT  ; ha ha!  Store will complete while the CPU is halted!

Some more-interesting code will be discussed in the final tutorial.

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