Simple three-bus CPU architecture

The above picture has a problem when used in a pipelined architecture in the case that one of the current instruction's operands is the same as the result of the last instruction, e.g. if they're both R3. In this case, if you recall the pipelining discussion, we will be doing the "operand fetch" of the new instruction in the same clock cycle in which we are doing the "store result" of the previous instruction. When you write to a register in the same cycle in which you're reading from it, the reading gets the register's old value. This means that in code like

ADD R1, R2, R3
ADD R3, R4, R5

Fortunately this problem can be solved by a mechanism entitled "operand forwarding". Operand forwarding involves pushing a result ahead in the pipeline, in the above exact case.

We connect the ALU operand either to the appropriate operand bus or to the result bus, as follows, using a multiplexer to make the selection in accordance with criteria described below:

The multiplexers' control inputs are as follows:

The left multiplexer's control input says "the current instruction's left operand is the same as the previous instruction's result". The right multiplexer's control input says "the current instruction's right operand is the same as the previous instruction's result". (They are thus independent, and can even both be on simultaneously.)

This is part of the "microprogramming notes" web pages, which contain the following subtopics:

1. Simple one-bus CPU architecture
2. Register in / out connections
3. Microcode examples
4. ALU architecture (insides)
5. ALU interface (outsides)
6. Control circuitry
7. Simple two-bus CPU architecture
8. Simple three-bus CPU architecture    <-- you are here